ET1810, ET1811 | EtherCAT IP core for Intel® FPGAs

The EtherCAT IP core enables the EtherCAT communication function and application-specific functions to be implemented on an FPGA (Field Programmable Gate Array – i.e. a device containing programmable logical components). The EtherCAT functionality is freely configurable. The IP core can be combined with own FPGA designs, and it can be integrated in System-on-Chips (SoCs) with soft core processors or hard processor systems via the Avalon® or AMBA® AXI™ interfaces. The physical interfaces and internal functions, such as the number of FMMUs and SYNC managers, the size of the DPRAM, etc., are adjustable. The process data interface (PDI) and the distributed clocks are also configurable. The functions are compatible with the EtherCAT specification and the ET1100 EtherCAT ASIC.

The ET1811 quantity-based licenses offer manufacturers of small lots and development service providers the possibility of entering the world of EtherCAT development with low initial investment. For the development of an EtherCAT device, the ET1811 one-time kick-off charge is required, plus the ET1811-1000 royalty for 1000 devices. The royalties for 1000 devices must be paid in advance each time.

For development service providers only the ET1811 one-time kick-off charge will be required; the ET1811-0030 system integrator OEM license will be required for each customer implementation. The end customer will be required to pay the royalty license (ET1811-1000).