Industrial flash memory devices for Beckhoff Industrial PCs

With pSLC storage technology, TLC cells are used as SLC cells via firmware. This means that only one bit is stored using two charge levels per memory cell. As a result, the service life is extended since minor charge shifts have no impact on the bit state of the memory cell. When reading out the memory cell, the two charge states, 0 and 1, are easier to recognize without errors than eight different charge levels of the TLC data storage. The switch from TLC to pSLC increases the service life of the memory cells by a factor of over 16, with P/E cycles increasing from 3,000 to 50,000.

By defining different charge levels of the charge trap layers, several bits can be stored in a single flash cell. With modern technology, up to four bits can be stored in a single cell. The different memory architectures are SLC, MLC, TLC, and QLC. With TLC memory cells, three bit states are stored in a single cell.

Flash memory cells are effectively MOSFET transistors with an additional layer. Insulated by an oxide layer, this charge trap layer can store charge on a non-volatile basis and preserve a bit state in the process. To program the memory cell, a high electrical voltage is applied to the control gate, which injects individual electrons from the channel layer into the charge trap layer. A reference voltage is applied to the control gate to read out the bit status. If the charge trap layer is charged, the charge counteracts the current flow through the transistor, which corresponds to bit state 0. If no charge is present in the charge trap layer, the current can flow through the transistor, indicating a bit state of 1.

When storing several bits in a memory cell, errors can occur when reading out the bit states, as the distances between the individual voltage levels are small. The more bit states are stored per cell, the shorter the service life of an SSD. What’s more, the number of read operations per memory cell increases, as several reference voltages have to be applied to read the bit status of a cell due to the different charge levels. This reduces the speed at which data is read out.

The application of high voltages means every write and erase operation degenerates the oxide layer, causing irreparable damage to the memory cell in the process. As a result, flash memory loses its reliable data storage properties over time. Another side effect is that the voltages applied when reading memory cells can negatively impact the charge state of neighboring cells.

The flat 2D NAND memory architecture reaches its capacity limits as data volumes increase. The high number of memory cells results in reduced spacing, which can cause interference and leakage currents between neighboring cells. The 3D NAND flash memory architecture makes it possible to increase the number of memory cells per area by stacking the planar structures vertically. This means that the storage capacity of an SSD can be significantly increased without affecting the service life of the flash cells.

Integration via the NVMe (Non-Volatile Memory Express) software protocol enables direct communication between the SSD and CPU via the high-speed PCIe socket so that the full performance of the SSD can be utilized. Using parallel PCIe lanes also ensures smooth data transfer and very low latency times. This reduces charging times, speeds up boot processes, and ensures smoother system performance overall.